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data sheet v02 16.6.99 TUA6110xs sat mixer-oscillator-pll consumer electronics
ausgabe 16.02.98 herausgegeben von in?neon ag igr, marketing-kommunikation, balanstra?e 73, 81541 mnchen ? in?neon ag igr 1999. alle rechte vorbehalten. wichtige hinweise! gew?hr fr die freiheit von rechten dritter leisten wir nur fr bauelemente selbst, nicht fr anwendungen, verfahren und fr die in bauelementen oder baugruppen realisierten schaltungen. mit den angaben werden die bauelemente spezi?ziert, nicht eigenschaften zugesichert. lieferm?glichkeiten und technische ?nderun- gen vorbehalten. fragen ber technik, preise und lieferm?gli- chkeiten richten sie bitte an den ihnen n?chst- gelegenen vertrieb halbleiter in deutschland oder an unsere landesgesellschaften im aus- land. bauelemente k?nnen aufgrund technischer erfordernisse gefahrstoffe enthalten. ausknfte darber bitten wir unter angabe des betreffenden typs ebenfalls ber den ver- trieb halbleiter einzuholen. die in?neon ag igr ist ein hersteller von cecc-quali?zierten produkten. verpackung bitte benutzen sie die ihnen bekannten verw- erter. wir helfen ihnen auch weiter C wenden sie sich an ihren fr sie zust?ndigen vertrieb halbleiter. nach rcksprache nehmen wir verpackungsmaterial sortiert zurck. die transportkosten mssen sie tragen. fr verpackungsmaterial, das unsortiert an uns zurckgeliefert wird oder fr das wir keine rcknahmep?icht haben, mssen wir ihnen die anfallenden kosten in rechnung stellen. bausteine in lebenserhaltenden ger?ten oder systemen mssen ausdrcklich dafr zugelassen sein! kritische bauelemente 1 des bereichs hal- bleiter der in?neon ag igr drfen nur mit aus- drcklicher schriftlicher genehmigung des bereichs halbleiter der in?neon ag igr in leb- enserhaltenden ger?ten oder systemen 2 eingesetzt werden. 1 ein kritisches bauelement ist ein in einem lebenserhaltenden ger?t oder system eingesetztes bauelement, bei dessen aus- fall berechtigter grund zur annahme besteht, da? das lebenserhaltende ger?t oder system ausf?llt bzw. dessen sicher- heit oder wirksamkeit beeintr?chtigt wird. 2 lebenserhaltende ger?te und systeme sind (a) zur chirurgischen einp?anzung in den menschlichen k?rper gedacht, oder (b) untersttzen bzw. erhalten das men- schliche leben. sollten sie ausfallen, besteht berechtigter grund zur annahme, da? die gesundheit des anwenders gef?hrdet werden kann. edition 16.02.98 published by in?neon ag igr, marketing-kommunikation, balanstr. 73, 81541 munich ? in?neon ag igr 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of compo- nent and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group of?ces in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for infor- mation on the types in question please contact your nearest in?neon of?ce, semiconductor group. in?neon ag igr is an approved cecc manu- facturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales of?ce. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of in?neon ag igr, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of in?neon ag igr. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effec- tiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasona- ble to assume that the health of the user may be endangered.
TUA6110xs revision history: current version: 16.6.99 previous version: 30.7.98 old page new page subjects (major changes since last revision) all all siemens logo change to in?neon logo data classi?cation maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise speci?ed, typical characteristics apply at t a = 25 c and the given supply voltage. operating range in the operating range the functions given in the circuit description are ful?lled. for detailed technical information about "processing guidelines" and "quality assurance" for ics, see our "product overview" .
table of contents page data sheet TUA6110xs wireless group 1 16.6.99 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pin con?guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.1 mixer-oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.2 pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.3.1 bit allocation read / write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9.3.2 i 2 c bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 ac / dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12.1 digital unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12.1.1 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12.1.2 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12.2 analog unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.2.1 mixer-oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.2.2 band a circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.2.3 band b circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.1 dc and rf parameter measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.2 measurement of crystal oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 equivalent i / o-schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 15.1 application circuit 1, band a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 15.2 application circuit 2, band b (evaluation board) . . . . . . . . . . . . . . . . . . . . . . . . . 22
data sheet tua 6110xs wireless group 1 16.6.99 1 features mixer/oscillator two 4 pin oscillator for band a and band b frequency range optimum decoupling of input frequency from oscillator double balanced mixer with wide dynamic range and low-impedance input for band a and band b frequency range internal low-noise reference voltage source pll pll with short lock-in time; no asynchro- nous divider stage fast i 2 c bus mode possible 3 programmable chip addresses short pull-in time for quick channel access and optimized loop stability 3 high-current switch outputs 2 ttl inputs 5-level a/d converter lock-in ?ag power-down ?ag few external components full esd protection 2 pinning tssop 28 3 ordering information type package ordering code tua 6110xs p-tssop-28-1 q67001-a5211 tua 6110xs p-tssop-28-1 tape & reel q67007-a5211l
data sheet TUA6110xs wireless group 2 16.6.99 4 functional description the tua 6110x device combines a mixer-oscillator block including two balanced mixers and two oscillators, with a digitally programmable phase locked loop (pll) for use in sat tuners. the mixer-ocillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for band a/band b and a low-noise reference volt- age source. the pll block with three hard-switched chip addresses forms a digitally programmable phase locked loop. with a 4 mhz quartz crystal, the pll permits precise setting of the frequency of the sattuner oscillator up to 3.3 ghz in increments of 125 khz. the tuning process is controlled by a microprocessor via an i 2 c bus. the device has three output ports, which all can also be used as input ports (two ttl inputs and one a/d con- verter input). a ?ag is set when the loop is locked. the input ports and lock ?ag can be read by the processor via the i 2 c bus. 5 application the ic is suitable for all sat-tuners in tv- and vcr-sets, cable set-top receivers and topset-converters for analog tv an digital video broadcasting.
data sheet TUA6110xs wireless group 3 16.6.99 6 pin con?guration p-tssop-28-1 p-tssop 28-1 1 mixa mixax 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v vcca scl cas ifout mixbx oa-b2 ob-e2 ob-e1 ob-b1 mixb gnd a 9 10 11 12 13 14 16 15 26 25 28 27 ifoutx gnd d sda v vccd q q x tune chgpmp p0 / i0 p1 / i1 p2 / adc oa-e2 oa-e1 oa-b1 ob-b2
data sheet TUA6110xs wireless group 4 16.6.99 7 pin description pin no. symbol function 1 mixa band a mixer input, low-impedance, symmetrical to mixax 2 mixax band a mixer input, low-impedance, symmetrical to mixa 3 mixb band b mixer input, low-impedance, symmetrical to mixbx 4 mixbx band b mixer input, low-impedance, symmetrical to mixb 5v vcca positive supply voltage for analog block 6 cas chip address select 7 ifout open collector mixer output, high-impedance, symmetrical to ifoutx 8 ifoutx inverse open collector mixer output, high-impedance, symmetrical to ifout 9 gnd d digital ground 10 sda data input/output for the i 2 c bus 11 scl clock input for the i 2 c bus 12 v vccd positive supply voltage for digital block (pll) 13 q 4 mhz low-impedance crystal oscillator input 14 qx inverse 4 mhz low-impedance crystal oscillator input 15 p2/adc port output / adc input 16 p1/i1 port output / ttl input 17 p0/i0 port output / ttl input 18 chgpmp charge pump output / loop ?lter 19 tune vco tuning voltage output 20 gnd a analog ground 21 ob-b1 band b oscillator ampli?er, high-impedance base input, symmetrical to ob-b2 22 ob-e1 band b oscillator ampli?er, low-impedance emitter output, symmetrical to ob-e2 23 ob-e2 band b oscillator ampli?er, low-impedance emitter output, symmetrical to ob-e1 24 ob-b2 band b oscillator ampli?er, high-impedance base input, symmetrical to ob-b1 25 oa-b1 band a oscillator ampli?er, high-impedance base input, symmetrical to oa-b2 26 oa-e1 band a oscillator ampli?er, low-impedance emitter output, symmetrical to oa-e2 27 oa-e2 band a oscillator ampli?er, low-impedance emitter output, symmetrical to oa-e1 28 oa-b2 band a oscillator ampli?er, high-impedance base input, symmetrical to oa-b1
data sheet TUA6110xs wireless group 5 16.6.99 8 block diagram vco vcox crystal oscillator ob-b2 ob-e2 ob-e1 ob-b1 oa-b2 oa-e2 oa-e1 28 27 26 25 24 23 22 mixer b 12345678 121314 mixb mixbx mixa mixax v vcca cas ifout ifoutx gnd d qx q 9 v vccd 10 11 sda scl i2c-bus interface i/o-ports phase- det.& chgpmp oa-b1 gnd a tune chgpmp p0/io p1/ i1 p2/adc 21 20 19 18 17 16 15 ref.- divider progr. divider cy f ref isolation ampli?er oscillator b mixer a isolation ampli?er oscillator a a/b
data sheet TUA6110xs wireless group 6 16.6.99 9 circuit description 9.1 mixer-oscillator block the mixer-oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for band a/band and a reference voltage source. in a complete tuner the input signal passes a frontend stage with mesfet amplifier, a double-tuned band- pass filter and is then fed to the balanced mixer input of the ic which has a low-impedance input. the input signal is mixed there with the on chip oscillator signal. 9.2 pll block the mixer-oscillator signal vco/vcox is internally dc-coupled as a differential signal at the programmable divider inputs. the signal subsequently passes through a programmable divider with ratio n = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency f ref = 125 khz. this frequency is derived from a balanced, low-impedance 4 mhz crystal oscillator (pin q, qx) divided by q = 32. the phase detector has two outputs up and down that drive two current sources i+ and i- of a charge pump. if the negative edge of the divided vco signal appears prior to the negative edge of the reference signal, the i+ current source pulses for the duration of the phase difference. in the reverse case the i- current source pul- ses. if the two signals are in phase, the charge pump output (chgpmp) goes into the high-impedance state (pll is locked). an active low-pass ?lter integrates the current pulses to generate the tuning voltage for the vco (internal ampli?er, external pullup resistor at tune and external rc circuitry). the charge pump output is also switched into the high-impedance state when the control bit t0 = 1. here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. tune may be switched off by the control bit os to allow external adjustments. if the vco is not working the pll locks to a tuning voltage of 33v. by means of control bit 5i the pump current can be switched between two values by software. this program- mability permits alteration of the control response of the pll in the locked-in state. in this way different vco gains can be compensated, for example. the software-switched ports p0, p1, p2 are general-purpose open-collector outputs. the test bit t1 = 1, switches the test signals f ref (4 mhz / 32) and c y (divided input signal) to p0 and p1 respectively. p0, p1, p2 are bidirectional. the lock detector resets the lock ?ag fl when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). hence, when fl = 1, the maximum deviation of the input fre- quency from the programmed frequency is given by d f = i p (k vco / f q ) (c 1 +c 2 ) / (c 1 c 2 ) where i p is the charge pump current, k vco the vco gain, f q the crystal oscillator frequency and c 1 , c 2 the capacitances in the loop ?lter (see application circuit). as the charge pump pulses at 125 khz (= f ref ), it takes a maximum of 16 m s for fl to be reset after the loop has lost lock state. once fl has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive f ref periods. therefore it takes between 128 and 144 m s for fl to be set after the loop regains lock.
data sheet TUA6110xs wireless group 7 16.6.99 9.3 i 2 c-bus interface data is exchanged between the processor and the pll via the i 2 c bus. the clock is generated by the proces- sor (input scl), while pin sda functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the i 2 c bus. the data from the processor pass through an i 2 c bus controller. depending on their function the data are sub- sequently stored in registers. if the bus is free, both lines will be in the marking state (sda, scl are high). each telegram begins with the start condition and ends with the stop condition. start condition: sda goes low, while scl remains high. stop condition: sda goes high while scl remains high. all further infor- mation transfer takes place during scl = low, and the data is forwarded to the control logic on the positive clock edge. the table 1 bit allocation should be referred to the following description. all telegrams are transmitted byte- by-byte, followed by a ninth clock pulse, during which the control logic returns the sda line to low (acknowl- edge condition). the ?rst byte is comprised of seven address bits. these are used by the processor to select the pll from several peripheral components (chip select). the lsb bit (r/w) determines whether data are written into (r/w = 0) or read from (r/w = 1) the pll. in the data portion of the telegram during a write operation, the msb bit of the ?rst or third data byte deter- mines whether a divider ratio or control information is to follow. in each case the second byte of the same data type has to follow the ?rst byte. if the address byte indicates a read operation, the pll generates an acknowledge and then shifts out the status byte onto the sda line. if the processor generates an acknowledge, a further status byte is output; oth- erwise the data line is released to allow the processor to generate a stop condition. the status word consists of two bits from the ttl input ports, three bits from the a/d converter, the lock ?ag and the power-on ?ag. three different chip addresses can be set by appropriate connection of pin cas (see table 2 address selection). when the supply voltage is applied, a power-on reset circuit prevents the pll from setting the sda line to low, which would block the bus. the power-on reset ?ag por is set at power-on and if v vccd falls below 3.2 v. it will be reset at the end of a read operation.
data sheet TUA6110xs wireless group 8 16.6.99 9.3.1 bit allocation read / write table1: divider ratio: n = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0 control bytes: bandswitch a/b: a/b=1 osc/mix band b is active ports p0, p1, p2: p0...p2=1open-collector output is active p0...p2=0open-collector output is inactive, ttl-inputs i1, i0 and adc available pump current 5i: 5i=1 high pd output current 5i=0 low pd output current disabling tuning voltage os: os=1 disables tune os=0 enables tune status byte: power on reset ?ag por: ?ag is set at power-on and reset at the end of read operation pll lock ?ag fl: ?ag is set to 1 when loop is locked ttl-inputs i1, i0: input data from pins p1/i1, p0/i0 adc bits a2,a1,a0: digital outputs of the 5-level adc byte msb 1) 1. ) msb shifted first. bit6 bit5 bit4 bit3 bit2 bit1 lsb ack remarks write data address byte 1 1 0 0 0 ma1 ma0 0 a progr. divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 a progr. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 a control byte 1 1 5i t1 t0 1 1 1 os a control byte 2 a/b x x x x p2 p1 p0 a read data address byte 1 1 0 0 0 ma1 ma0 1 a status byte por fl x i1 i0 a2 a1 a0 a
data sheet TUA6110xs wireless group 9 16.6.99 table 2: address selection table 3: test modes table 4: a/d converter levels voltage at cas ma1 ma0 (0...0.1) * v vcc 00 (0.4...0.6) * v vcc 10 (0.9...1) * v vcc 11 test mode t1 t0 normal operation 0 0 p1 = cy output, p0 = f ref output 1 0 charge pump output, chgpmp is in high-impedance state 0 1 ttl-inputs i1/i0 are cy/f ref inputs of phase detector 1 1 voltage at p2 / adc a2 a1 a0 (0...0.15) * v vcc 000 (0.15...0.3) * v vcc 001 (0.3...0.45) * v vcc 010 (0.45...0.6) * v vcc 011 (0.6...1) * v vcc 100
data sheet TUA6110xs wireless group 10 16.6.99 9.3.2 i 2 c bus timing diagram note: sda scl ack. ack. 2nd byte 1st byte 3rd byte ack. ack. addressing ma1 r/w ma0 telegram examples: start-addr-dr1-dr2-cw1-cw2-stop start= start condition start-addr-cw1-cw2-dr1-dr2-stop addr= address byte start-addr-dr1-dr2-stop dr1= prog. divider byte 1 start-addr-cw1-cw2-stop dr2= prog. divider byte 2 cw1= control byte 1 cw2= control byte 2 stop= stop condition 4th byte
data sheet TUA6110xs wireless group 11 16.6.99 10 absolute maximum ratings the maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the ic will result. ambient temperature under bias: t a =-20 to +80 c parameter symbol limit values unit test conditions min max pll supply voltage v vccd -0.3 +6 v chgpmp v chgpmp i chgpmp -0.3 1 v ma crystal oscillator pins q, qx v q i q -5 v vccd v ma bus input/output sda bus output current sda v sda i sda(l) -0.3 +6 5 v ma bus input scl v scl -0.3 +6 v port outputs p0, p1, p2 v p -0.3 +13 v chip address switch cas v cas -0.3 v vccd v vco tuning output (loop ?lter) v tune -0.3 +35 v bus output sda i sdal -1 5 ma open collector port outputs p0, p1, p2 i p(l) -1 15 ma open collector total port output current s i p(l) 20 ma t max = 0,1 sec. at 6 v junction temperature t j +125 c storage temperature t stg -40 +125 c thermal resistance (junction to ambient) r thsa 130 k/w
data sheet TUA6110xs wireless group 12 16.6.99 all values are referred to ground (pin), unless stated otherwise. currents with a positive sign ?ows into the pin and currents with a negative sign ?ows out of pin. mixer-oscillator supply voltage v vcca -0.3 +6 v mix a/b inputs v mixa/b i mixa/b -5 2 6 v ma vco a/b base voltage v oa/b-b -0.3 3 v vco a/b emitter current i oa/b-e -5 5 ma if output v ifout v ifoutx 6v parameter symbol limit values unit test conditions min max esd-protection 1 1. according to mil std 883d, method 3015.7 and eos/esd assn. standard s5.1 - 1993 all pins unless otherwise speci?ed v esd -1 1 kv mixer inputs mixa/b v esd mix -500 500 v pin 1-4 mixer outputs ifout / ifoutx v esd if -500 500 v pin 7, 8 ports v esd p -500 500 v pin 15-17 charge pump v esd cp -500 500 v pin 18 oscillator inputs oa/ob v esd osc -500 500 pin 21-28 parameter symbol limit values unit test conditions min max
data sheet TUA6110xs wireless group 13 16.6.99 11 operating range within the operational range the ic operates as described in the circuit description. the ac / dc characteristic limits are not guaranteed. parameter symbol limit values unit test conditions min max supply voltage v vccd +4.5 +5.5 v supply voltage v vcca +4.5 +5.5 v mixer output voltage v ifout v ifoutx +4.5 +5.5 v open collector programmable divider factor n 256 32767 mixer a input frequency range f mixa 420 920 mhz oscillator a frequency range f oa 900 1400 mhz mixer b input frequency range f mixb 900 2150 mhz oscillator b frequency range f ob 1400 2650 mhz ambient temperature t amb -20 +80 c
data sheet TUA6110xs wireless group 14 16.6.99 12 ac / dc characteristics supply voltage v vcca = 5 v, v vccd = 5 v ambient temperature t amb = 25 c parameter symbol limit values unit test conditions min typ max 12.1 digital unit 12.1.1 pll supply current i vccd 21 26 31 ma v vccd = 5 v crystal oscillator connections q, qx crystal frequency f q 3.2 4.0 4.8 mhz series resonance crystal resistance r q 10 100 w series resonance oscillation frequency f q 3,99975 4,000 4,00025 mhz f q = 4 mhz input impedance z q -600 -750 -900 w f q = 4 mhz charge pump output chgpmp high output current i cph 90 220 300 m a 5i = 1, v cp = 2 v low output current i cpl 22 50 75 m a 5i = 0, v cp = 2 v tristate current i cpz +1 na t0 = 1, v cp = 2 v output voltage v cp 1.0 2.5 v locked drive output tune (open collector) high output current i th 10 m av th = 33 v, t0 = 1 low output voltage v tl 0.5 v i tl = 1.0 ma 12.1.2 i 2 c-bus bus inputs scl, sda high input voltage v ih 3 5.5 v low input voltage v il 0 1.5 v high input current i ih 10 m av ih = v s low input current i il -10 m av il = 0 v bus output sda (open collector) high output current i oh 10 m av oh = 5.5 v low output voltage v ol 0.4 v i ol = 3 ma edge speed scl,sda rise time t r 300 ns fall time t f 300 ns clock timing scl frequency f scl 0 400 khz high pulse width t h 0.6 m s low pulse width t l 1.3 m s start condition set-up time t susta 0.6 m s hold time t hsta 0.6 m s
data sheet TUA6110xs wireless group 15 16.6.99 stop condition set up time t susto 0.6 m s bus free t buf 1.3 m s data transfer set-up time t sudat 0.1 m s hold time t hdat 0 m s input hysteresis scl, sda v hys 200 mv pulse width of spikes which are suppressed t sp 050ns capacitive load for each bus line c l 400 pf port outputs p0, p1, p2 (open collector) high output current i poh 1 m av poh = 5 v low output voltage v pol 0.5 v i pol = 15 ma ttl port inputs p0, p1 high input voltage v pih 2.7 v low input voltage v pil 0.8 v high input current i pih 10 m av pih = 13.5 v low input current i pil -10 m av pil = 0 v adc port input p2 high input current i adch 10 m a low input current i adcl -10 m a address selection input cas high input current i cash 50 m av cash = 5 v low input current i casl -50 m av casl = 0 v parameter symbol limit values unit test conditions min typ max
data sheet TUA6110xs wireless group 16 16.6.99 12.2 analog unit 12.2.1 mixer-oscillator current consumption i vcca 14 20 26 ma bit a/b=0 i vcca 14 20 26 ma bit a/b=1 mixer current i if 468ma mixer output impedance r ifout 11 k w parallel equivalent circuit, f if = 479,5 mhz c ifout 0.5 pf parallel equivalent circuit, f if = 479,5 mhz 12.2.2 band a circuit section mixer input impedance r mixa 20 w f mixa = 950 mhz l mixa 10 nh f mixa = 950 mhz oscillator frequency range f osca 900 1400 mhz v d = 0,5..28 v oscillator drift d f osca 2 mhz v s = 5 v 10% d f osca 2 mhz d t = 25 c d f osca 5 mhz t = 5 s up to 15 min after switching on oscillator phase noise l(fm) -78 dbc/hz fm = 10 khz, application circuit 1 mixer gain g mixa 368db f mixa = 420 mhz (dsb), f if =479.5mhz g mixa 368db f mixa = 920 mhz (dsb), f if =479.5mhz mixer noise ?gure f mixa 81013db f mixa = 420 mhz (dsb), f if =479.5mhz f mixa 81013db f mixa = 920 mhz (dsb), f if =479.5mhz if suppression a ifb 20 db v mixa = 80 db m v parameter symbol limit values unit test conditions min typ max
data sheet TUA6110xs wireless group 17 16.6.99 12.2.3 band b circuit section mixer input impedance r mixb 20 w f mixb = 950 mhz l mixb 10 nh f mixb = 950 mhz oscillator frequency range f oscb 1400 2650 mhz v d = 0,5..28 v oscillator drift d f oscb 2 mhz v s = 5 v 10% d f oscb 2 mhz d t = 25 c d f oscb 5 mhz t = 5 s up to 15 min after switching on oscillator phase noise l(fm) -65 dbc/hz fm = 10 khz, application circuit 2 mixer gain g mixb 368db f mixb = 950 mhz (dsb), f if =479.5mhz g mixb 23db f mixb = 2150 mhz (dsb), f if =479.5mhz mixer noise ?gure f mixb 81013db f mixb = 950 mhz (dsb), f if =479.5mhz f mixb 15 18 db f mixb = 2150 mhz (dsb), f if =479.5mhz if suppression a ifb 20 db v mixb = 80 db m v parameter symbol limit values unit test conditions min typ max
data sheet TUA6110xs wireless group 18 16.6.99 13 test circuit 13.1 dc and rf parameter measurement bb833 bb833 4.7n 15 16 17 18 19 20 21 22 23 24 25 26 27 28 22k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 4 2 5 47p 47p tua 6110xs balun v vcca if output sda scl v vccd 10n 18p 22p 22p 22k 4.7n 33k 27k 8.2n 1.8n 4mhz +33v 220 220 cas 6.8p balun: toko b4f 617db-1023 100p 100p 100n 4.7n 22k 22k bb545 bb545 5.6p 5.6p 22k 4.7n 22k 22k 1 4 2 5 47p 47p balun 6.8p
data sheet TUA6110xs wireless group 19 16.6.99 13.2 measurement of crystal oscillator frequency 4 mhz i vcc 5v p0 18 pf counter tua 6110xs gnd d v vcc 5 k q f ref test mode: t1 = high t0 = low f q = f ref * 32 p1 counter f vco = f cy * n n: divider ratio f cy 5 k
data sheet TUA6110xs wireless group 20 16.6.99 14 equivalent i / o-schematic 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14
data sheet TUA6110xs wireless group 21 16.6.99 15 application circuits 15.1 application circuit 1, band a 22k bb545 bb545 1n 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tua 6110xs v vcca if output sda scl v vccd 4.7n 18p 5.6p 5.6p 22k 1n 1n 33k 22k 22n 2.2n 4mhz +33v 220 220 cas 132n 1n +5v 2.7k 2.7k 2.7k 8.2 printed 4.7n 100p 100p 4.7n 4.7n 4.7n 100k 22k 22p 22p 2.2p 3.3p 33 33
data sheet TUA6110xs wireless group 22 16.6.99 15.2 application circuit 2, band b (evaluation board) 22k bb835 bb835 4.7n 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 4 2 5 47p 47p tua 6110xs balun v vcca if output sda scl v vccd 4.7n 18p 22p 22p 100 4.7n 6.8p 33k 27k 8.2n 1.8n 4mhz +33v 220 220 cas 10u 6.8p +5v 2.7k 2.7k 2.7k 8.2 printed balun: toko b4f 617db-1023 4.7n 100p 100p 4.7n 4.7n stripline l=7.0mm w=0.75mm 4.7n 100k stripline l=7.0mm w=0.75mm note: pcb material: fr4, h=1.25mm

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